Increase your VHDL proficiency by learning advanced techniques that will help you write more robust and reusable code. This comprehensive course is targeted toward designers who already have some experience with VHDL. The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.

Software Tools

• Xilinx ISE
• Mentor Graphics ModelSim PE

Skills Gained

After completing this training, you will be able to:

• Write efficient and reusable RTL, testbenches, and packages
• Create self-testing testbenches
• Create realistic models
• Use the Text IO capabilities of VHDL
• Store data dynamically
• Create parameterized designs

• VHDL users with introductory to intermediate knowledge of VHDL

• Introduction to VHDL course OR equivalent knowledge of modeling, simulation, and RTL coding
• At least 6 months of coding experience beyond an introductory course