Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE tool suite and Xilinx hardware. Eight labs provide hands-on experience in this two-day course and cover Synplicity’s Synplify, Mentor’s Precision, and the Xilinx XST tools. This course requires the Fundamentals of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended, as is at least sixMonths’ design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE software tools and the Virtex-II and Virtex-4 FPGAs.

Software Tools

• Xilinx ISE™
• Synplicity® Synplify Pro™ Precision
• Xilinx XST

Skills Gained

After completing this training, you will be able to:

• Create and edit constraints for hand-placing logic and creating timing constraints
• Build Relationally Placed Macros (RPMs) to improve performance on critical paths
• Run the Xilinx Implementation software from the command line
• Use incremental design techniques in addition to Floorplanner to implement a “divide and conquer” methodology
• Optimize post-Place & Route designs in the FPGA Editor for more efficient in-circuit testing and minor modifications

Lab Descriptions

• Lab 1: Timing Analyzer, Constraints, and Closure – Create global timing constraints, read timing reports, apply path-specific constraints (multicycle and false paths), and apply advanced implementation options.
• Lab 2: UCF – Write constraints directly into a UCF file to guide the performance results of implementation.
• Lab 3: Scripting – Write program commands into a batch file to implement the design. Then modify program switches to obtain the greatest possible performance from the design.
• Lab 4: RPM – Create an RPM in a UCF file. Use the Timing Analyzer to find a path that is not meeting timing constraints and identify the components of that path. RLOC the components to create the RPM and improve timing for that path.
• Lab 5: Divide and Conquer Design Techniques – Use incremental design techniques and Floorplanner for effective implementation of “divide and conquer” techniques.
• Lab 6: FPGA Editor – Use the FPGA Editor to view and edit a design. Analyze the contents of a CLB; add a probe; remove, place, and modify components; and analyze long nets.
• Lab 7: Reduce Clock Period – Use all of your obtained knowledge to reduce the clock period delay.

• Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilization while also increasing productivity

• Fundamentals of FPGA Design
• Designing for Performance
• Intermediate knowledge of Verilog or VHDL is strongly recommended
• At least six months’ design experience with Xilinx tools and FPGAs