Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.

Software Tools

• ISE™
• Synplicity® Synplify Pro™
• Mentor Graphics® Precision RTL™

Skills Gained

After completing this training, you will be able to:

• Describe a flow for obtaining timing closure
• Describe architectural features of the Virtex™-4 FPGA
• Describe the features of the Digital Clock Manager (DCM) and Phase-Matched Clock Divider (PMCD) and how they can be used to improve performance
• Increase performance by duplicating registers and pipelining
• Write HDL code by using a style that is optimal for targeting Xilinx device
• Describe different synthesis options and how they can improve performance
• Create and integrate cores into your design flow by using the CORE Generator™ software system
• Run behavioral simulation on an FPGA design that contains cores
• Pinpoint design bottlenecks by using the Timing Analyzer reports
• Apply advanced timing constraints to meet your performance goals
• Use advanced implementation options to increase design performance

• FPGA designers with intermediate knowledge of HDL and some experience with the Xilinx ISE software tools.

• Fundamentals of FPGA Design course or equivalent knowledge of FPGA architecture features; the Xilinx implementation software flow and implementation options; reading timing reports; basic FPGA design techniques; global timing constraints and the Constraints Editor
• Intermediate HDL knowledge (VHDL or Verilog)
• Solid digital design background