 |
|
|
|
Learn how to employ
RocketIO GTP serial transceivers in your Virtex-5 LXT FPGA design. Understand
and utilize the features of the RocketIO transceiver blocks, such as CRC, 8B/10B
encoding, channel bonding, clock correction, and comma detection. Additional
highlighted topics include use of the Architecture Wizard and synthesis and
implementation considerations. This course balances lecture modules and
practical hands-on labs.
Software Tools
- ISE™
- Mentor Graphics ModelSim PE
Skills Gained
After completing this training, you will be able to:
- Describe and utilize
the ports and attributes of the RocketIO multi-gigabit transceiver (GTP) in the
Virtex-5 LXT FPGA
- Effectively use the
following features of the GTP
- Comma detection,
CRC, clock correction, and channel bonding
- 8B/10B
encoding/decoding, programmable termination and preemphasis
- Use the GTP Wizard
to instantiate GTP primitives in a design
- Access appropriate
reference material for board design issues
- Power supply,
oscillators, and trace design
|
|
|
 |
- Introduction
- Clocking and Resets
- 8B/10B Encoder and
Decoder Details
- Lab 1: 8B/10B
Disparity and Bypass Commas and Data Alignment Details
- Lab 2: Commas and
Data Alignment Cyclical Redundancy Check Details
- Lab 3: Cyclical
Redundancy Check Clock Correction Details
- Lab 4: Clock
Correction Channel Bonding Details
- Lab 5: Channel
Bonding GTP Wizard Overview
- Implementing a
RocketIO Transceiver Design
- Lab 6: Synthesis and
Implementation Physical Media Attachment Overview
|
|
- Lab 1: 8B/10B Disparity and Bypass – Utilize the 8B/10B encoder
and decoder and observe running disparity. Learn how to bypass the 8B/10B
encoder and decoder.
- Lab 2: Commas and
Data Alignment – Use programmable comma detection to align a serial data stream.
- Lab 3: CRC –
Configure a CRC block using the CRC Wizard.
- Lab 4: Clock
Correction – Utilize the clock correction logic to compensate for frequency
differences on the TX and RX side of a link.
- Lab 5: Channel
Bonding – Modify a design to use two transceivers bonded together to form one
virtual channel.
- Lab 6: Synthesis and
Implementation – Use the GTP Wizard to configure RocketIO transceiver
primitives. Instantiate the resulting component in a design, synthesize the
design, and implement the design.
|
|
|
 |
 |
 |
- FPGA designers and logic designers
|
|
|
 |
|
|
- Verilog or VHDL experience (or the Introduction to Verilog or the Introduction
to VHDL course)
- Synthesis and simulation experience FPGA design experience or the Fundamentals of FPGA Design course
- Knowledge of high-speed serial I/O protocols and standards (SONET, Gigabit
Ethernet, InfiniBand, etc.) is a plus
|
 |
 |
|
|
|
|
|
|
|
|
|
|
|