Interested in learning how to effectively utilize Virtex-5 FPGA architectural resources? Targeted towards experienced Xilinx users who have already completed Fundamentals of FPGA Design and Designing for Performance and have a comprehensive knowledge of Virtex-4 FPGAs, this course focuses on understanding as well as designing into several of the new and enhanced resources found in our newest device. Topics covered include a Virtex-5 FPGA overview, new LUT, DCM and PLL, global and regional clocking techniques, memory, DSP and arithmetic logic, and source-synchronous resources. A combination of modules and labs allow for practical hands-on application of the principles taught.

Software Tools

• ISE™
• Synplicity Synplify Pro
• Mentor Graphics Precision

Skills Gained

After completing this training, you will be able to:

• Describe and utilize new Virtex-5 FPGA resources, including:
• 6-input LUT
• DCM and PLL
• Global and regional clock resources
• Memory resources
• Arithmetic and DSP resources

• For those who have taken the Fundamentals of FPGA Design and Designing for Performance courses.
• A comprehensive knowledge of the Virtex-4 family architecture is also required. This material should be considered a Virtex-5 FPGA update course from the Virtex-4 FPGA family.

• Fundamentals of FPGA Design course
• Designing for Performance course
• Designing with the Virtex-4 Family course
• Comprehensive knowledge of the Virtex-4 FPGA