• Introduction Virtex-5 Technology
  • Virtex-5 Families
• ISE Design Tool
  • Tool enhancements for Virtex-5 support
• Powering and Packaging
  • Modifications and enhancements
• Virtex-5 Configuration
  • Modifications and enhancements
• Clocking Resources
  • Comparison Virtex IIPro/Virtex-4 - Virtex-5
  • New Clock Manager Technology
  • DCM modifications
  • Phase Lock Loops
  • Global and regional clock networks
  • Application examples
• I/O Resources
  • Comparison Virtex IIPro/Virtex-4 - Virtex-5
  • Modifications on IOBs
  • New I/O standards
• Core Resources
  • Comparison Virtex IIPro/Virtex-4 - Virtex-5
  • 6-input LUT
  • RAMB36: Block RAM application examples and Block RAM ECC
  • FIFO36 and application examples
  • XtremeDSP48E Slice, features and application examples
  • Embedded EMAC core (*)
  • Embedded PCI Express core (*)
  • GTR transceivers (*)
  • GTX transceivers und PowerPC 440 core
• Labs
  • Clocking resources: PLL
  • Core resources: 6-input LUT
  • RAM/FIFO
  • XtremeDSP48E
  • Serial I/O example (*)

Course content

• Introduction and Content
• Virtex-5 FPGA Overview
  • Virtex-5 FPGA Introduction
  • Architecture Enhancements
• Software Support for Virtex-5
  • Introduction
  • Partitioning
  • Interactive Tcl Console
  • Timing Closure Environment
  • XST Improvements
• Clocking Resources
  • Introduction
  • Clock Management Tile
  • Clock Networks
  • Use Examples
• Phase Locked Loop
  • PLL Functional Description
  • PLL Attributes
  • Application Examples
  • PLL Usage
• Quick Reference
  • Clocking Constraints and Primitives
• Lab 1: PLL Resources
• Configurable Logic Block
  • 6-input LUT with Dual Output
  • Slice Configurations
  • CLB Interconnect
• Quick Reference
  • CLB Constraints and Primitives
• Lab 2: CLB
• I/O Resources
  • I/O General Architecture
  • IOB Architecture
  • ChipSync Architecture
• Quick Reference
  • I/O Constraints

• Lab 3: I/O SERDES and Regional Clocks
• Block RAM Memory Resources
• FIFO Memory Resources
  • FIFO18 / FIFO36
• Block RAM Integrated Error Correction
• Quick Reference:
  • Block RAM and FIFO Constraints
• Lab 4: RAM Design
• DSP48E Technology Resource
  • XtremeDSP Technology Slice Features
  • Slice Features Special Details
  • DSP48E Slice
  • Application Examples
  • DSP48E Usage
• Quick Reference
  • DSP48E ALU- and OP-Modes
• Lab 5: DSP48E Resource
• EMAC Embedded Core
  • Embedded TEMAC Overview
  • Architecture of the Virtex-5 Ethernet MAC
  • Configuration Options
  • Physical Interface
  • Differences Virtex-4 / Virtex-5 EMAC
  • Core Generator Tools
• PCI Express Introduction
  • PCI Express Basics
  • PCI Express Topology
• PCI Express Endpoint Core
  • PCIe Endpoint Block Overview
    • Architecture
    • Interfaces
    • Register Overview
    • Attributes Overview
  • PCIe Block Function and Compliance
  • Designing with the PCI Express Wizard
  • Application Tips
• GTP Overview
  • Virtex-5 Solutions
  • Ease of Use
  • Standards Support
  • Virtex Family Rocket IO Differences
• GTP Transceiver Architecture and Functionality
  • GTP Tile
  • GTP Transmitter
  • GTP Receiver
  • Resets
  • CRC
  • Loopback
• GTP Usage
  • Ports and Attributes
  • Instantiation vs. RocketIO Wizard
  • Simulation
  • Implementation
  • Verification (CSP / IBERT)
  • GTP Board Design
  • GTP Link Analysis
  • Application Example: Backplane
• Lab6: GTP
• Serial I/O: GTX
• PowerPC 440 Embedded Core
• System Monitor Resource
  • Architecture and Operation
  • Application Guidelines Overview
  • Use Models and Design Tools
• Power and Packaging
  • Virtex-5 Power
    • Static Power Reduction
    • Dynamic Power Reductions
    • Power Estimation
  • Virtex-5 Packaging
  • Simultaneously Switching Outputs
• Configuration
  • Virtex-5 Legacy Support
  • Virtex-5 New Configuration Features
  • Serial Configuration: SPI Interface
  • Parallel Configuration: BPI Interface
  • Systems with Multiple Bitstreams
  • Design Security