Use the ISE™ software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow. This course covers ISE features, such as the Architecture Wizard and the Pin and Area Constraint Editor (PACE). Other topics include design planning, implementation options, and global timing constraints. Learn about project structure, process windows, various ISE software design flows, and Xilinx Synthesis Technology (XST). You will examine XST synthesis and use the XST constraints file in the Project Navigator GUI. You will learn about the Engineering Capture System (ECS) and the StateCAD and ISE Simulator tools.

Software Tools

• ISE™

Skills Gained

After completing this training, you will be able to:

• Create and use a new Xilinx Project Navigator in the ISE software to implement an FPGA design.
• Assign pin locations with the PACE tool
• Create DCM instantiations with the Architecture Wizard
• Read reports to determine whether design goals were met
• Use the Constraints Editor to enter basic global timing constraints
• Locate and modify implementation options

• Digital designers who have a working knowledge of HDL (VHDL or Verilog). Who are new to Xilinx FPGAs and use ISE software extensively and need to learn the major aspects of the new ISE product

• Basic FPGA Architecture
• Working HDL knowledge (VHDL or Verilog)
• Digital design understanding