By learning PCI Express core protocol fundamentals, designers can gain a working knowledge of how PCI Express can be used in their systems. This course focuses on the PCI Express protocol subjects that designers, using the Xilinx PCI Express core should understand to complete their designs faster and easier. Students will also be introduced to Xilinx PCI Express core product and will gain intimate knowledge of how the PCI Express core operates. This course covers the implementation of a Xilinx PCI Express system with supporting logic and example designs. Xilinx PCI Express core products will be enumerated to aid you in selecting the proper solution. This course focuses on the Virtex-5 FPGA PCIe Endpoint Block Plus and the Spartan-3 PCIe integrated Endpoint PIPE block.

Software Tools

• Xilinx ISE 9.2i
• ISIM 9.2i
• ChipScopePro9.2i

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Construct a basic PCIe system
• Select the appropriate core for your application
• Specify and design an example endpoint application
• Connect the PCIe core with the user endpoint functionality
• Utilize FPGA resources to support the core
• Simulate the design
• Develop a software application to drive an endpoint
• Software engineers who want to understand the deeper workings of the Xilinx LogiCORE PCI Express solution
• Identify the advanced capabilities of the PCIe specification protocol and feature set

• Hardware designers who want to create applications using Xilinx IP cores for PCI Express
• Software engineers who want to understand the deeper workings of the Xilinx LogiCORE PCI Express solution
• System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications

• Comprehensive understanding of the PCIe protocol (2 hour review included)
• Solid knowledge of Verilog or VHDL
• Solid experience with commonly used simulation tools such as Mentor Graphics ModelSim or ISIM
• Basic knowledge of Xilinx ISE™ software
• Designing for Performance and Designing with Multi-Gigabit Serial I/O are recommended