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The 3-day workshop “Signal Integrity and Board Design” is aimed at developers
who want to implement high-speed interfaces between a XILINX FPGA and external
semiconductor components and who want to design complex high-speed FPGA at board
level. This Workshop is designed for developers who not only design FPGAs but
also systems and the layout.
The first part of this course tackles the signal integrity issues in general.
You will learn to judge when signal integrity is important and relevant, to
interpret, for example, IBIS models, and to select appropriate termination
procedures. Signal refection and crosstalk effects are described and
demonstrated by simulation. Simulation examples are given for common memory
interfaces as well as for MGT interconnection. You will learn how to implement
high-speed buses, including clock design, loading and signal termination.
Furthermore, the power distribution and bypassing design are main topics.
The second part of this course covers the board design. With the availability of
the Virtex-4 and Virtex-5 families, FPGA designers face new implementation
possibilities and challenges.
Many different interfaces to external components allow a vast variety of
application areas. The high data rates that Virtex-4 and Virtex-5 are able to
handle require in depth knowledge about the physical design around the FPGA.
Based on the power requirements of the FPGA, solutions for power supplies are
presented. Termination schemes that are necessary for high clock and data rates
are discussed broadly. In that context the different signal levels and
termination variations are covered. A special chapter discusses the clock supply
as well as connecting to high speed components on the board. Moreover, rules for
designing PCBs will be commented on.
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