Learn how signal integrity techniques are applicable to high-speed interfaces between Xilinx FPGAs and semiconductor memories. This course teaches you about high-speed bus and clock design, including transmission line termination, loading, and jitter. You will work with IBIS models and complete simulations using CAD packages. You will also discuss topics that include managing PCB effects and on-chip termination. This course balances lecture modules and practical hands-on labs.

Software Tools

• Mentor Graphics HyperLynx
• Cadence SPECCTRAQuest

Skills Gained

After completing this training, you will be able to:

• Identify when signal integrity is important and relevant
• Interpret an IBIS model and correct common errors
• Apply appropriate transmission line termination
• Understand the effect loading has on signal propagation
• Mitigate the impact of jitter
• Manage a memory data bus
• Understand the impact of selecting a PCB stackup
• Differentiate between on-chip termination and discrete termination

• Digital designers, board layout designers, or scientists, engineers, and technologists seeking to implement Xilinx solutions.
•  End users of Xilinx products who want to understand how to implement high-speed interfaces without incurring the signal integrity problems related to timing, crosstalk, and overshoot or undershoot infractions.

• Xilinx FPGA design experience preferred (equivalent of Fundamentals of FPGA Design course)