This comprehensive hands-on intensive course provides complete and integrated training program. It is structured as a comparison between traditional Verilog 1995 and newer Verilog standards 1364-2001 and 1800-2005 SystemVerilog. The goal of this course is to fulfill the needs and requirements for engineers, who want to exploit wide breadth of SystemVerilog features for both design and verification.

Skills Gained

After completing this training, you will be able to:

• Use Verilog 2001 and SystemVerilog design advanced techniques
• Create reusable parameterized designs and verification models
• Create libraries and configurations
• Build abstract models for verification of digital designs, using class-based object oriented constructs
• Create random, coverage driven simulation environment
• Discuss SystemVerilog IEEE-1800 assertions

• Experienced Verilog design and verification engineers who want to use Verilog 1364-2001 and SystemVerilog 1800-2005 features for modeling, synthesis and verification of digital designs

• Digital design knowledge, Verilog 1364-1995