This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lecture with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001. In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Software Tools

• Synopsys SmartModels
• ISE™

• Xilinx ISIM Simulator

Skills Gained

After completing this training, you will be able to:

• Write RTL Verilog code for synthesis
• Write Verilog test fixtures for simulation
• Create a Finite State Machine (FSM) by using Verilog
• Target and optimize FPGAs by using Verilog
• Run a timing simulation by using Xilinx Simprim libraries
• Create and manage designs by using the ISE software design environment
• Implement Verilog 2001 language enhancements

• Basic digital design knowledge