This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course. In this course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Software Tools

• Xilinx ISE
• Xilinx ISIM Simulator
• Synplicity Synplify Pro
• Synopsys SmartModels

Skills Gained

After completing this training, you will be able to:

• Use VHDL to build hardware models
• Declare and use signals, variables, arrays, and records
• Use VHDL process statements
• Create synthesizable RTL source code
• Run a behavioral simulation, pre- and post-P&R
• Synthesize (compile to hardware) VHDL using XST
• Run a timing simulation using VITAL libraries
• Write FPGA-optimized code for RAMs, FSMs, etc.
• Synthesize RTL code and implement a design in Xilinx FPGAs
• Create VHDL subprograms, functions, and procedures

• Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs

• Basic digital design knowledge